Publications

Thèses de doctorat:

  1. Arwa Ben Dhia (Direction Lirida Naviner), Hardening Basic Blocks in a Mesh of Clusters FPGA, Télécom ParisTech, 14/11/2014.
  2. Saif ur Rehman (Direction Mounir Benabdenbi et Lorena Anghel, Conception en vue du test et du diagnostic de FPGA tolérants aux défauts de fabrication, TIMA, juin 2015.
  3. Adrien Blanchardon (Direction Habib Mehrez et Roselyne Chotin-Avot), Synthèse d’architectures de circuits FPGA tolérants aux défauts, UMPC-LIP6, mai 2015.

Livre:

  1. Arwa Ben Dhia and Lirida Naviner, Designing a Robust Mesh of Clusters FPGA: Hardening basic blocks, LAP LAMBERT Academic Publishing (January 14, 2015), ISBN-10: 3659662836, ISBN-13: 978-3659662836

Journaux scientifiques :

  1. Arwa Ben Dhia, M. Slimani, H. Cai and L. A. B. Naviner, A dual-rail compact defect-tolerant multiplexer, Microelectronics Reliability Journal, March 2015, vol. 55, pp. 662-670 [hal-01128326].
  2. Ben Dhia, S. Nascimento Pagliarini, L. Alves de Barros Naviner, H. Mehrez and Ph. Matherat, A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs, Microelectronics Reliability, July 2013, pp. 1189–1193 [hal-01062109].

Conférences scientifiques internationales :

  1. A. Ben Dhia, M. Slimani and L. Alves de Barros Naviner, Comparative Study of Defect-Tolerant Multiplexers for FPGAs, 20th IEEE International On-Line Testing Symposium (IOLTS), Platja d’Aro, Spain, July 2014, pp. 7-12 [hal-01062059].
  2. A. Ben Dhia, M. Slimani and L. A. B. Naviner, A Defect-Tolerant Multiplexer Using Differential Logic for FPGAs, IEEE 21st Mixed Design of Integrated Circuits and Systems Conference (MIXDES), Lublin, Poland, June 2014, pp. 375-380 [hal-01062063].
  3. M. Slimani, A. Ben Dhia et L. A. B. Naviner, Cross Logic : A New Approach for Defect-Tolerant Circuits, IEEE International Conference on IC Design and Technology (ICICDT), Austin, USA, Mai 2014, pp. 1-4 [hal-01062064].
  4. A. Ben Dhia, M. Slimani and L. Alves de Barros Naviner, Improving the Robustness of a Switch Box in a Mesh of Clusters FPGA, 15th IEEE Latin American Test Workshop (LATW), Fortaleza, Brazil, March 2014, pp. 1-6 [hal-01062066].
  5. Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, and Zied Marrakchi. Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. In Proceedings of International Conference on Recongurable Computing and FPGAs(ReConFig), Cancun, Mexico, December 2013.
  6. A. Ben Dhia, Saif Ur Rehman, Adrien Blanchardon, Lirida Alves de Barros Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri, and Zied Marrakchi. A defect-tolerant cluster in a mesh sram-based fpga. In Proceedings of International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013.
  7. A. Ben Dhia, S. Nascimento Pagliarini, L. Alves de Barros Naviner, H. Mehrez and Ph. Matherat, A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Arcachon, France, October 2013, pp. 1189–1193 [hal-01062075]. mj
  8. Saif ur Rehman, Mounir Benabdenbi, and Lorena Anghel. BIST for logic and local interconnect resources in a novel mesh of cluster fpga. In Proceedings of IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, New York, USA, October 2013.
  9. A. Ben Dhia, L. Alves de Barros Naviner and Ph. Matherat, Evaluating CLB Designs under Multiple SETs in SRAM-based FPGAs, IEEE Symp. Defect and Fault Tolerance (DFT), New-York City, United States, October 2013, pp. 112-117 [hal-01062101].
  10. Saif ur Rehman, Mounir Benabdenbi, and Lorena Anghel. Test time reduction methodology for a cluster FPGA. In South European Test Seminar, Tirol, Austria, 2013.
  11. A. Ben Dhia, L. Alves de Barros Naviner and Ph. Matherat, Comparison of Fault-Tolerant Fabless CLBs in SRAM-based FPGAs, IEEE Latin-American Test Workshop (LATW), Cordoba, Argentina, April 2013, pp. 1-6 [hal-01062112].
  12. A. Ben Dhia, L. Alves de Barros Naviner and P. Matherat, A New Fault-Tolerant Architecture for CLBs in SRAM-based FPGAs, IEEE International Conference on Electronics, Circuits, and Systems (ICECS) , Sevilla, Spain, December 2012, pp. 761-764 [hal-01062116].
  13. A. Ben Dhia, L. Alves de Barros Naviner and P. Matherat, Analyzing and Alleviating the Impact of Errors on an SRAM-based FPGA Cluster, IEEE International On-Line Testing Symposium (IOLTS), Sitges, Spain, June 2012, pp. 31-36 [hal-01062799].
  14. A. Blanchardon, R. Chotin-Avot, H. Mehrez and E. Amouri, Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy, Field Programmable Logic and Applications (FPL), 2014 , Munich, Germany, pages 1-4
  15. A. Blanchardon, R. Chotin-Avot, H. Mehrez and E. Amouri, Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA, ReConFigurable Computing and FPGAs (ReConFig), 2014, Cancun, Mexico, pages 1-6
  16. Saif-Ur Rehman, Mounir Benabdenbi and Lorena Anghel, Test and diagnosis of FPGA cluster using partial reconfiguration, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Grenoble, 2014 , june, page: 1 – 4
  17. Saif-Ur Rehman, Mounir Benabdenbi and Lorena Anghel, Cost-efficient Testing of a cluster in a mesh SRAM-based FPGA, IEEE Online Test Symposium (IOLTS), 2014, Platja d’Aro, Spain, pages: 75 – 80
  18. Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi, Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, pages: 553 – 558
  19. Saif Ur Rehman, Mounir Benabdenbi, and Lorena Anghel, Application-independent Testing of Multilevel Interconnect in Mesh-based FPGAs, IEEE Design and Technology of Integrated Systems Conference (DTIS), 2015, april, Napoli, Italy, pages : à paraître

Colloques scientifiques nationaux:

  1. Arwa Ben Dhia, L. Alves de Barros Naviner et Ph. Matherat, Nouvelle architecture de BLE tolérante aux fautes dans les FPGAs SRAM, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM), Grenoble, France, Juin 2013.
  2. Saif ur Rehman, Mounir Benabdenbi, and Lorena Anghel. Cost-effient testing of LUT and intra-cluster interconnect of a novel sram-based fpga. In Colloque SoC-SiP, Lyon, France, 2013.
  3. Arwa Ben Dhia, L. Alves de Barros Naviner et P. Matherat, Tolérance aux défauts dans les FPGAs, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM), Marseille, France, Juin 2012.
  4. Adrien Blanchardon, Roselyne Chotin-Avot, and Habib Mehrez. G’en’erateur d’architectures fpga. In Colloque SoC-SiP, Paris, France, June 2012.
  5. Saif Rehman, Mounir Benabdenbi, and Lorena Anghel. Fpga: Design for test and diagnosis. In Ecole d’Hiver FETCH, Alpes d’Huez, France, January 2012.